The New Product Design process often benefits from the use of FPGAs and other programmable logic.
By more highly integrating designs and utilizing the most secure
and advanced programmable and reconfigurable digital, analog, and mixed signal devices, the product development process can be temporally shortened
and design flexibility may be retained all the way to production.
These new hardware devices, combined with the proper use of high level design languages, such as Verilog and VHDL, allow for a level of flexibility
far beyond that available only a few years ago. Additional gate capacities have lead to the the concept of SOC (System On Chip), and FPSOC (Field Programmable
System On Chip).
Recent advances in device integration have allowed the propagation of reconfigurable
devices including both FPGAs and microcontrollers, that encompass a wide variety of common board level functions. The use of such devices has had a
significant positive effect on new product development
efforts. Rather than adding components and complexity to the design, these components reduce design overhead in a surprising number of ways:
- Reduced component count for simplified BOM.
- Reduced PCB space requirements.
- Increased design revision capability.
- Use of the same devices across multiple products or designs increases purchasing power and simplifies inventory requirements.
- Enhanced design re-use capabilities.
- Simplified R&D through programmable elements.
- Use of similar tools across devices and products reduces engineer educational efforts.
Time Tested Product Development Techniques
Today's reconfigurable devices have progressed well beyond the FPGA and PAL technologies that proliferated during the 1990's and now include mixed
signal hybrid devices such as the Motorola
56800E core-based family
of Hybrid Controllers, which combine the processing power of a DSP and the functionality
of a microcontoller inside a compact 64-pin LQFP.
This device features 60 MIPS performance (at 60 MHz), along with 48 KB of on-chip Flash memory
and a comprehensive set of peripehrals. It extends the capabilities of the
by adding additional analog-to-digital converter (ADC) inputs,
and timer input/output pins.
A second device family of note, the
Cypress PSoC CY8C27x,
contains over 100 reconfigurable analog and digital library components created from 12 fundamental analog and 8 digital blocks.
Each of these PSoC (Programmable System on Chip) devices contain a 24 MHz 8-bit microcontroller unit (MCU);
16 kbytes of flash memory; 256 bytes of SRAM; an 8x8 multiplier with 32-bit accumulator; power and sleep monitoring circuits;
and a precision real-time clock. The largest device in the family, the
contains many resource ideal for use in combination with FPGAs.
Since the devices have a defined set of analog and digital resources,
that can be configured in many ways
the overall device function is determined entirely by its programmable configuration.
As a result, there are little or no "clues to function" provided by a visual
examination of the PCB.
Many devices, including both the Motorola and Cypress parts
have security features to prevent configuration readback. The reconfigurability
of the devices allow for a tampering defense through "configuration scrubbing", or the
loading of "white" configurations.
Other configurable devices with analog/digital functions:
16-Kbyte self-programming Flash Program Memory, 1-Kbyte SRAM, 512 Byte EEPROM, 8 Channel 10-bit A/D-converter. JTAG interface for on-chip-debug. 4 X 25 Segment LCD Driver. Up to 16 MIPS throughput at 16 MHz. 5 Volt Operation.
"Butterfly" Development Kit)
The MSP430 family consists of several devices featuring different sets of peripherals targeted for various applications.
The devices employ five low power modes and feature a 16-bit RISC CPU, 16-bit registers, digitally controlled oscillator (DCO),
allowing wake-up from low-power modes to active mode in < 6Ás.
The MSP430xW42x series are microcontroller configurations with two built-in 16-bit timers, a comparator, 96 LCD segment drive capability,
a scan interface, and 48 I/O pins.